Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET

K. Murata, T. Otsuji, M. Ohhata, M. Togashi, E. Sano, M. Suzuki

研究成果: Paper査読

19 被引用数 (Scopus)

抄録

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.

本文言語English
ページ193-196
ページ数4
出版ステータスPublished - 1994 12月 1
外部発表はい
イベントProceedingsof the 1994 IEEE GaAs IC Symposium - Philadelphia, PA, USA
継続期間: 1994 10月 161994 10月 19

Other

OtherProceedingsof the 1994 IEEE GaAs IC Symposium
CityPhiladelphia, PA, USA
Period94/10/1694/10/19

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル