Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS

S. Kubicek, A. Veloso, K. G. Anil, S. Hayashi, K. Yamamoto, R. Mitsuhashi, A. Kittl, M. Lauwers, S. Van Dal, Horii, Y. Harada, M. Kubota, M. Niwa, S. De Gendt, M. Heyns, M. Jurczak, S. Biesemans

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

We show for the first time that full Ni silicidation (Ni-FUSI) of poly gates in combination with Hf based gate dielectrics meets the required device performance for the 65nm LSTP technology node. Important device parameters, like Cinv, mobility and drive currents exhibit significant improvement without compromising the oxide integrity and reliability. The drive of nMOS and pMOS transistors for the VDD=1.1V at 10pA/μm off state leakage is 575μA/ μm and 1650 μA/μm respectively.

本文言語English
ホスト出版物のタイトル2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
ページ99-100
ページ数2
DOI
出版ステータスPublished - 2005 10 31
外部発表はい
イベント2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH - Hsinchu, Taiwan, Province of China
継続期間: 2005 4 252005 4 27

出版物シリーズ

名前2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Other

Other2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
国/地域Taiwan, Province of China
CityHsinchu
Period05/4/2505/4/27

ASJC Scopus subject areas

  • 工学(全般)

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