抄録
In this paper, a three-dimensional (3-D) memory array architecture is proposed. This new architecture is realized by stacking several cells in series vertically on each cell located in a two-dimensional array matrix. Therefore, this memory array architecture has a conventional horizontal row and column address and new vertical row address. The total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM when one bit-line has 1-Kbit cells and the same design rules are used. Moreover, an array area of 1-Mbit DRAM using the proposed architecture is reduced to 11.5% of normal DRAM using the same design rules. This proposed architecture's DRAM can realize small bit-line capacitance and small array area simultaneously. Therefore, this proposed 3-D memory array architecture is suitable for future ultrahigh-density DRAM.
本文言語 | English |
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ページ(範囲) | 476-483 |
ページ数 | 8 |
ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | 34 |
号 | 4 |
DOI | |
出版ステータス | Published - 1999 4月 |
ASJC Scopus subject areas
- 電子工学および電気工学