New three dimensional (3D) memory array architecture for future ultra high density DRAM

T. Endoh, H. Sakuraba, K. Shinmei, F. Masuoka

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

Three dimensional (3D) memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in two dimensional (2D) array matrix. Total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM, when one bit-line has 1K-bit cells and the same design rules are used. Moreover, array area of 1M-bit DRAM using the proposed architecture, is reduced to 11.5% of normal DRAM using the same design rules.

本文言語English
ホスト出版物のタイトル2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
出版社IEEE
ページ447-450
ページ数4
ISBN(印刷版)0780352351, 9780780352353
出版ステータスPublished - 1999 1 1
イベント22nd International Conference on Microelectronics (MIEL 2000) - Nis, Yugoslavia
継続期間: 2000 5 142000 5 17

出版物シリーズ

名前2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
2

Other

Other22nd International Conference on Microelectronics (MIEL 2000)
CityNis, Yugoslavia
Period00/5/1400/5/17

ASJC Scopus subject areas

  • 工学(全般)

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