New reconfigurable memory architecture for parallel image-processing LSI with three-dimensional structure

Shigeo Kodama, Daijirou Amano, Takeaki Sugimura, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

研究成果: Article査読

4 被引用数 (Scopus)

抄録

A reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed. The proposed memory network can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data. In addition, a specification of the data bandwidth between PEs and the proposed memory network can be changed in the synchronization with single instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD) operations. Therefore, data transfer has greater flexibility. Also, from the result of the performance evaluation by implementation into the field programmable gate array (FPGA), it was successfully shown that the proposed memory network reduced the execution time by up to 28.2% for a 9 × 9 filtering operation.

本文言語English
ページ(範囲)2774-2778
ページ数5
ジャーナルJapanese journal of applied physics
47
4 PART 2
DOI
出版ステータスPublished - 2008 4月 25

ASJC Scopus subject areas

  • 工学(全般)
  • 物理学および天文学(全般)

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