New multichip-to-wafer 3D integration technology using Self-Assembly and Cu nano-pillar hybrid bonding

Mitsumasa Koyanagi, Kanuku Ri, T. Fukushima, T. Tanaka

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

New 3D integration technology using self-assembly and Cu nano-pillar hybrid bonding are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Many known good dies (KGDs) are simultaneously self-assembled with a high alignment accuracy making use of liquid surface tension in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier and electrostatically bonded by applying a voltage to bipolar electrodes on the SAE carrier. The self-assembled dies on the carrier are simultaneously transferred to another wafer or interposer wafer by electrostatically debonding the carrier wafer after Cu nano-pillar hybrid bonding of self-assembled dies.

本文言語English
ホスト出版物のタイトル2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings
編集者Ru Huang, Ting-Ao Tang, Yu-Long Jiang
出版社Institute of Electrical and Electronics Engineers Inc.
ページ338-341
ページ数4
ISBN(電子版)9781467397179
DOI
出版ステータスPublished - 2016 1 1
イベント13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Hangzhou, China
継続期間: 2016 10 252016 10 28

出版物シリーズ

名前2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings

Other

Other13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016
CountryChina
CityHangzhou
Period16/10/2516/10/28

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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