Multiple-valued VLSI architecture for intra-chip packet data transfer

Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama

研究成果: Conference article査読

2 被引用数 (Scopus)


A packet data transfer scheme is introduced for intra-chip data transfer to solve an interconnection problem. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. The total number of packets in a micronetwork can be reduced by multiplexing two binary packets into a single multiple-valued packet, which makes the micronetwork throughput very high. The multiplexing can be realized by liner summation of two packets in current-mode logic. Moreover, multiple-valued source-coupled logic is introduced in the router circuit. Thus, we can design the very high-speed micronetwork using current-mode multiple-valued logic.

ジャーナルProceedings of The International Symposium on Multiple-Valued Logic
出版ステータスPublished - 2005 9 20
イベント35th International Symposium on Multiple-Valued Logic, ISMVL 2005 - Calgary, Alta., Canada
継続期間: 2005 5 192005 5 21

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

フィンガープリント 「Multiple-valued VLSI architecture for intra-chip packet data transfer」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。