Multiple-valued logic-in-memory VLSI based on ferroelectric capacitor storage and charge addition

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama

研究成果: Conference article査読

2 被引用数 (Scopus)

抄録

A multiple-valued logic-in-memory VLSI using ferroelectric capacitors is proposed to realize an arithmetic-oriented VLSI with real-time programmable capacitor storage. The use of a remnant-polarization charge on a ferroelectric capacitor makes it possible to perform not only a real-time programmable storage function, but also a linear-sum function, thereby resulting in a compact hardware while maintaining a high-speed processing capability. As a design example, a full adder with a storage capability is evaluated. Its performance is superior to that of a corresponding binary CMOS implementation.

本文言語English
ページ(範囲)161-166
ページ数6
ジャーナルProceedings of The International Symposium on Multiple-Valued Logic
出版ステータスPublished - 2002 1 1
イベント32nd IEEE International Symposium on Multiple-Valued Logic - Boston, MA, United States
継続期間: 2002 5 152002 5 18

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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