Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network

T. Hanyu, K. Teranishi, M. Kameyama

研究成果: Conference article査読

18 被引用数 (Scopus)

抄録

A logic-in-memory structure, in which storage functions are distributed over a logic-circuit plane, is described. This structure is perceived as a solution to the communication bottleneck between memory and logic modules. This logic-in memory VLSI based on floating-gate MOS transistors merges storage and switching functions in a multiple-valued-input and binary output combinational logic circuit that is useful for the realization of parallel arithmetic and logic circuits.

本文言語English
ページ(範囲)194-195, 437
ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
出版ステータスPublished - 1998 1 1
イベントProceedings of the 1998 IEEE 45th International Solid-State Circuits Conference, ISSCC - San Francisco, CA, USA
継続期間: 1998 2 51998 2 7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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