A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput interleavers between variable and check nodes without clock-distribution problems are highly advantageous. Since control signals and data from mutual nodes are multiplexed using a multi-level dual-rail code-word, the number of communication steps can be greatly reduced, which results in high-speed communication without any additional wires. The hardware is simply implemented by utilizing a multiple-valued current-mode circuit because all the information can be superposed on the same line. The advantages of the proposed asynchronous data-transfer scheme are discussed in comparison with corresponding synchronous and conventional asynchronous schemes.
|ジャーナル||Proceedings of The International Symposium on Multiple-Valued Logic|
|出版ステータス||Published - 2005 9 20|
|イベント||35th International Symposium on Multiple-Valued Logic, ISMVL 2005 - Calgary, Alta., Canada|
継続期間: 2005 5 19 → 2005 5 21
ASJC Scopus subject areas
- Computer Science(all)