Multi-Pillar Surrounding Gate Transistor (M-SGT) for Compact and High-Speed Circuits

In order to realize compact and high-speed circuits for future ultra-high-density LSI's without reducing the feature size, we propose a Multi-pillar Surrounding Gate Transistor (M-SGT). The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode is surrounding the crowded multi-pillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. We have succeeded in fabricating the M-SGT CMOS inverter chain. The propagation delay reduces to 40%, compared with the planar transistor inverter chain. Owing to the high shrinkage and high-speed features, the M-SGT is extremely attractive for future high-speed ULSI devices.