TY - JOUR
T1 - Multi-Context TCAM-Based Selective Computing
T2 - Design Space Exploration for a Low-Power NN
AU - Arakawa, Ren
AU - Onizawa, Naoya
AU - DIguet, Jean Philippe
AU - Hanyu, Takahiro
N1 - Funding Information:
Manuscript received April 17, 2020; revised July 22, 2020 and September 5, 2020; accepted October 1, 2020. Date of publication October 21, 2020; date of current version December 21, 2020. This work was supported in part by JSPS KAKENHI under Grant JP16H06300 and in part by the VLSI Design and Education Center, The University of Tokyo, with Synopsys Corporation. This article was recommended by Associate Editor T. Serrano-Gotarredona. (Corresponding author: Ren Arakawa.) Ren Arakawa, Naoya Onizawa, and Takahiro Hanyu are with Tohoku University, Sendai 980-8577, Japan (e-mail: ren.arakawa.t3@dc.tohoku.ac.jp).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2021/1
Y1 - 2021/1
N2 - In this paper, we propose a low-power memory-based computing architecture, called selective computing architecture (SCA). It consists of multipliers and an LUT (Look-Up Table)-based component, that is multi-context ternary content-addressable memory (MC-TCAM). Either of them is selected by input-data conditions in neural-networks (NNs). Compared with quantized NNs, a higher accurate multiplication can be performed with low-power consumption in the proposed architecture. If input data stored in the MC-TCAM appears, the corresponding multiplication results for multiple weights are obtained. The MC-TCAM stores only shorter length of input data, resulting in achieving a low-power computing. The performance of the SCA is determined by three physical parameters concerning the configuration of MC-TCAM. The power dissipation of the target NN can be minimized by exploring these parameters in the design space. The hardware based on the proposed architecture is evaluated using TSMC 65 nm CMOS technology and MTJ model. In the case of speech command recognition, the power consumption at the multiplication of the first convolutional layer in a convolutional NN is reduced by 67% compared to the solution relying only on multipliers.
AB - In this paper, we propose a low-power memory-based computing architecture, called selective computing architecture (SCA). It consists of multipliers and an LUT (Look-Up Table)-based component, that is multi-context ternary content-addressable memory (MC-TCAM). Either of them is selected by input-data conditions in neural-networks (NNs). Compared with quantized NNs, a higher accurate multiplication can be performed with low-power consumption in the proposed architecture. If input data stored in the MC-TCAM appears, the corresponding multiplication results for multiple weights are obtained. The MC-TCAM stores only shorter length of input data, resulting in achieving a low-power computing. The performance of the SCA is determined by three physical parameters concerning the configuration of MC-TCAM. The power dissipation of the target NN can be minimized by exploring these parameters in the design space. The hardware based on the proposed architecture is evaluated using TSMC 65 nm CMOS technology and MTJ model. In the case of speech command recognition, the power consumption at the multiplication of the first convolutional layer in a convolutional NN is reduced by 67% compared to the solution relying only on multipliers.
KW - Neural networks
KW - VLSI
KW - look-up table
KW - memory-based computing
KW - ternary content-addressable memory
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U2 - 10.1109/TCSI.2020.3030104
DO - 10.1109/TCSI.2020.3030104
M3 - Article
AN - SCOPUS:85093700810
SN - 1549-8328
VL - 68
SP - 67
EP - 76
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 1
M1 - 9234692
ER -