Superscalar and VLIW architectures are based on instruction-level parallelism (ILP), which ideally achieve high performance to execute multiple instructions in parallel. However, the system performance is restricted because of the Von Neumann bottleneck. Therefore, the memory hierarchy design is very important in this kind of architecture. We have proposed a computer architecture named Jetpipeline, which can execute both vector and scalar instructions in parallel. To make full use of the computing ability of Jetpipeline, this paper presents the memory hierarchy design for Jetpipeline and evaluates the effect of the design on the system performance of Jetpipeline through simulations.
|出版ステータス||Published - 1997 1 1|
|イベント||Proceedings of the 1997 2nd Aizu International Symposium on Parallel Algorithms/Architecture Synthesis - Fukushima, Jpn|
継続期間: 1997 3 17 → 1997 3 21
|Other||Proceedings of the 1997 2nd Aizu International Symposium on Parallel Algorithms/Architecture Synthesis|
|Period||97/3/17 → 97/3/21|
ASJC Scopus subject areas
- Computer Science(all)