抄録
Hierarchical approaches using multi-resolution images are well-known techniques to reduce the computational amount without degrading quality. One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. The complexity of the interconnection network mainly depends on memory allocation; it maps pixels onto memory modules and determines the required number of memory modules. This paper presents a memory allocation method to minimize the number of memory modules for image processing using multi-resolution images. For efficient search, the proposed method exploits the regularity of window-type image processing. A practical example demonstrates that the number of memory modules is reduced to less than 14% that of conventional methods.
本文言語 | English |
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ページ(範囲) | 2386-2397 |
ページ数 | 12 |
ジャーナル | IEICE Transactions on Information and Systems |
巻 | E91-D |
号 | 10 |
DOI | |
出版ステータス | Published - 2008 10月 |
ASJC Scopus subject areas
- ソフトウェア
- ハードウェアとアーキテクチャ
- コンピュータ ビジョンおよびパターン認識
- 電子工学および電気工学
- 人工知能