Memory allocation for multi-resolution image processing

Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama

研究成果: Article査読

4 被引用数 (Scopus)

抄録

Hierarchical approaches using multi-resolution images are well-known techniques to reduce the computational amount without degrading quality. One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. The complexity of the interconnection network mainly depends on memory allocation; it maps pixels onto memory modules and determines the required number of memory modules. This paper presents a memory allocation method to minimize the number of memory modules for image processing using multi-resolution images. For efficient search, the proposed method exploits the regularity of window-type image processing. A practical example demonstrates that the number of memory modules is reduced to less than 14% that of conventional methods.

本文言語English
ページ(範囲)2386-2397
ページ数12
ジャーナルIEICE Transactions on Information and Systems
E91-D
10
DOI
出版ステータスPublished - 2008 10月

ASJC Scopus subject areas

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • コンピュータ ビジョンおよびパターン認識
  • 電子工学および電気工学
  • 人工知能

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