Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator

N. Azuma, S. Shimazaki, N. Miura, M. Nagata, T. Kitamura, S. Takahashi, M. Murakami, K. Hori, A. Nakamura, K. Tsukamoto, M. Iwanami, E. Hankui, Sho Muroga, Y. Endo, Satoshi Tanaka, M. Yamaguchi

研究成果: Conference contribution

14 被引用数 (Scopus)

抄録

Substrate noise coupling in RF receiver front end circuitry for LTE wireless communication was examined by full-chip level simulation and on-chip measurements, with a demonstrator built in a 65 nm CMOS technology. A complete simulation flow of full-chip level substrate noise coupling uses a decoupled modeling approach, where substrate noise waveforms drawn with a unified package-chip model of noise source circuits are given to mixed-level simulation of RF chains as noise sensitive circuits. The distribution of substrate noise in a chip and the attenuation with distance are simulated and compare with the measurements. The interference of substrate noise at the 17th harmonics of 124.8 MHz - the operating frequency of the CMOS noise emulator creates spurious tones in the communication bandwidth at 2.1 GHz.

本文言語English
ホスト出版物のタイトルEMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits
出版社IEEE Computer Society
ページ42-46
ページ数5
ISBN(印刷版)9781479923151
DOI
出版ステータスPublished - 2013 1 1
イベント9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2013 - Nara, Japan
継続期間: 2013 12 152013 12 18

出版物シリーズ

名前EMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits

Other

Other9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2013
CountryJapan
CityNara
Period13/12/1513/12/18

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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