Lowering error floors in stochastic decoding of ldpc codes based on wire-delay dependent asynchronous updating

Stochastic decoding provides ultra-low-complexity hardware for high-throughput parallel low-density parity-check (LDPC) decoders. Asynchronous stochastic decoding was pro- posed to demonstrate the possibility of low power dissipation and high throughput in stochastic decoders, but decoding might stop before convergence due to 'lock-up', causing error floors. In this paper, we introduce wire-delay dependent asynchronous stochastic decoding to reduce the error floors. Instead of assigning the same delay to all computation nodes in the previous work, different computation delay is assigned to each computation node depending on its wire length. The variation of update timing increases switching activities to decrease the possibility of the 'lock-up', lowering the error floors. BER performance using a regular (1024, 512) (3, 6) LDPC code is simulated based on our timing model that has computation and wire delays estimated under ASPLA 90nm CMOS technology. It is demonstrated that the proposed asynchronous decoder achieves an up to 0.25-dB gain compared with that of the synchronous and the conventional asynchronous decoders.