Low resistivity bcc-Ta/TaNx metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450°C

H. Shimada, I. Ohshima, S. I. Nakao, M. Nakagawa, K. Kanemoto, M. Hirayama, S. Sugawa, T. Ohmi

研究成果: Paper査読

15 被引用数 (Scopus)

抄録

We have developed a low-resistivity metal gate Metal-Nitride-Semiconductor (MNS) FET technology having conventional plane gate structure featuring fully low-temperature processing. The gate stack consists of directly grown Silicon Nitride (Si3N4) dielectric using high-density plasma and bcc-phase Tantalum (∼15μΩcm) / Tantalum Nitride (bcc-Ta/TaNx) stacked metal gate below 1.0ohm/sq. In order to avoid deteriorating the metal gate system, we adopted a low-temperature S/D annealing by Solid Phase Epitaxy (SPE) method. In this paper, we demonstrate an excellent characteristic of Fully-Depleted Silicon-On-Dielectric (FDSOI) metal gate MNSFETs having conventional plane gate structure featuring fully low-temperature processing below 450°C.

本文言語English
ページ67-68
ページ数2
出版ステータスPublished - 2001 1 1
イベント2001 VLSI Technology Symposium - Kyoto, Japan
継続期間: 2001 6 122001 6 14

Other

Other2001 VLSI Technology Symposium
国/地域Japan
CityKyoto
Period01/6/1201/6/14

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

フィンガープリント

「Low resistivity bcc-Ta/TaNx metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450°C」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル