Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits

Nobuaki Okada, Michitaka Kameyama

研究成果: Article査読

2 被引用数 (Scopus)

抄録

A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A 4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.

本文言語English
ページ(範囲)619-631
ページ数13
ジャーナルJournal of Multiple-Valued Logic and Soft Computing
13
4-6
出版ステータスPublished - 2007 11 29

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Logic

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