TY - JOUR

T1 - Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits

AU - Okada, Nobuaki

AU - Kameyama, Michitaka

PY - 2007/11/29

Y1 - 2007/11/29

N2 - A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A 4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.

AB - A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A 4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.

KW - Direct allocation of control/data flow graph

KW - Fine-grain reconfigurable VLSI

KW - Low-power VLSI design

KW - Multiple-valued VLSI

KW - Multiple-valued source-coupled logic

KW - Universal literal

UR - http://www.scopus.com/inward/record.url?scp=36348954957&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=36348954957&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:36348954957

VL - 13

SP - 619

EP - 631

JO - Journal of Multiple-Valued Logic and Soft Computing

JF - Journal of Multiple-Valued Logic and Soft Computing

SN - 1542-3980

IS - 4-6

ER -