Low-power motion-vector detection VLSI processor based on pass-gate logic with dynamic supply-voltage/clock-frequency scaling

Akira Mochizuki, Nishinohara, Takahiro Hanyu

研究成果: Article査読

抄録

A new circuit technique based on pass-gate logic with dynamic supply-voltage and clock-frequency control is proposed for a low-power motion-vector detection VLSI processor. Since the pass-gate logic style has potential advantages that have small equivalent stray capacitance and small number of short-circuit paths, its circuit implementation makes it possible to reduce the power dissipation with maintaining high-speed switching capability. In case the calculation result is obtained on the way of calculation steps, additional power saving is also achieved by combining the pass-gate logic circuitry with a mechanism that dynamically scales down the supply voltage and the clock frequency while maintaining the calculation throughput. As a typical example, a sum of absolute differences (SAD) unit in a motion-vector detection VLSI processor is implemented and its efficiency in power saving is demonstrated.

本文言語English
ページ(範囲)1876-1883
ページ数8
ジャーナルIEICE Transactions on Electronics
E87-C
11
出版ステータスPublished - 2004 11月

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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