Low-power field-programmable VLSI processor using dynamic circuits

Weisheng Chong, Masanori Hariyama, Michitaka Kameyama

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

This paper proposes a low-power field-programmable VLSI processor (FPVLSI) to overcome the problem of large power consumption infield-programmable gate arrays (FPGAs). A bit-serial pipeline architecture is used in the FPVLSI to reduce the complexity of interconnection blocks. Moreover, a dual-supply-voltage scheme is effectively used to scale down the supply voltage along non-critical paths to obtain low power consumption without degrading the over-all speed performance. Its main drawback is the additional hardware cost of level converters to connect a low-supply-voltage module with a high-supply-voltage one. To solve this problem, a level-converter-less look-up table based on dynamic circuits is presented. The dynamic circuits are also useful to reduce glitch power that is one of the significant portions of the total power in FPGAs. The FPVLSI is designed based on a 0.18-μm CMOS design rule. The power consumption of the FPVLSI is reduced to 40% compared to that of the FPGA.

本文言語English
ホスト出版物のタイトルProceedings - IEEE Computer Society Annual Symposium on VLSI
ホスト出版物のサブタイトルEmerging Trends in VLSI Systems Design
編集者A. Smailagic, M. Bayoumi
ページ243-248
ページ数6
出版ステータスPublished - 2004 9 24
イベントProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States
継続期間: 2004 2 192004 2 20

出版物シリーズ

名前Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Other

OtherProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
CountryUnited States
CityLafayette, LA
Period04/2/1904/2/20

ASJC Scopus subject areas

  • Engineering(all)

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