Low-power dual-rail multiple-valued current-mode logic circuit using multiple input-signal levels

Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama

研究成果: Conference article査読

5 被引用数 (Scopus)

抄録

A new high-speed and low-power threshold detector is proposed to realize high-performance arithmetic VLSI systems. In a conventional threshold detector with a single supply voltage, the input signal swing of a differential-pair circuit (DPC) is too large, which causes large power dissipation together with a long switching delay. The use of two kinds of supply voltages makes the input signal swing of the DPC small, which results in a lower power dissipation together with a higher switching speed. As a typical example of the proposed multiple-valued current-mode (MVCM) logic circuit, a radix-2 signed-digit full adder is designed by using a 0.35-μm CMOS technology. Its performance is superior to that of a corresponding MVCM logic circuit with a single supply voltage under the same transistor counts.

本文言語English
ページ(範囲)382-387
ページ数6
ジャーナルProceedings of The International Symposium on Multiple-Valued Logic
出版ステータスPublished - 2000 1月 1
イベントISMVL'2000 - 30th IEEE International Symposium on Multiple-Valued Logic - Portland, OR, USA
継続期間: 2000 5月 232000 5月 25

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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