Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks

Naoya Onizawa, Warren J. Gross

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

We propose a novel architecture for low-power area-efficient large-scale IP lookup engines. The proposed architecture greatly increases memory efficiency by storing associations between IP addresses and their output rules instead of storing these data themselves. The rules can be determined by simple hardware using a few associations read from SRAMs, eliminating a power-hungry search of input addresses in TCAMs. The proposed hardware that stores 100,000 144-bit entries is evaluated under TSMC 65nm CMOS technology. The dynamic power dissipation and the area of the proposed hardware are 4.6% and 30.6% of a traditional TCAM, respectively while maintaining comparable throughput.

本文言語English
ホスト出版物のタイトルProceedings of the 50th Annual Design Automation Conference, DAC 2013
DOI
出版ステータスPublished - 2013 7 12
外部発表はい
イベント50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States
継続期間: 2013 5 292013 6 7

出版物シリーズ

名前Proceedings - Design Automation Conference
ISSN(印刷版)0738-100X

Conference

Conference50th Annual Design Automation Conference, DAC 2013
国/地域United States
CityAustin, TX
Period13/5/2913/6/7

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 制御およびシステム工学
  • 電子工学および電気工学
  • モデリングとシミュレーション

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