TY - JOUR
T1 - Low-energy asynchronous interleaver for clockless fully parallel LDPC decoding
AU - Onizawa, Naoya
AU - Gaudet, Vincent C.
AU - Hanyu, Takahiro
N1 - Funding Information:
Manuscript received June 30, 2010; revised November 05, 2010; accepted December 15, 2010. Date of publication February 14, 2011; date of current version July 27, 2011. This work was supported by the Japan Science and Technology Agency (JST), Core Research for Evolutional Science and Technology (CREST). This simulation was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence and Synopsys, Inc. This paper was recommended by Associate Editor Xinmiao Zhang.
PY - 2011
Y1 - 2011
N2 - This paper presents a low-energy asynchronous interleaver for clockless fully parallel low-density parity-check (LDPC) decoding. The proposed data-transmission circuit based on a half-duplex single-track protocol makes it possible to realize a wire-efficient asynchronous interleaver with small energy consumption. Moreover, a data-monitoring system adaptively shuts down the asynchronous data-transmission circuit if not necessary, which reduces the number of data transmissions and, hence, the energy consumed. The clockless decoder with the proposed asynchronous interleaver is evaluated using a (1056,528) irregular LDPC code under a 90-nm CMOS process. As a result, the energy dissipation per uncoded bit at Eb/No of 5 dB becomes 54 pJ/bit with an uncoded throughput of 45.5 Gbps under a postlayout simulation. This represents a 92% decrease in energy per bit and a 1143% in throughput increase with respect to our previous clockless LDPC decoder.
AB - This paper presents a low-energy asynchronous interleaver for clockless fully parallel low-density parity-check (LDPC) decoding. The proposed data-transmission circuit based on a half-duplex single-track protocol makes it possible to realize a wire-efficient asynchronous interleaver with small energy consumption. Moreover, a data-monitoring system adaptively shuts down the asynchronous data-transmission circuit if not necessary, which reduces the number of data transmissions and, hence, the energy consumed. The clockless decoder with the proposed asynchronous interleaver is evaluated using a (1056,528) irregular LDPC code under a 90-nm CMOS process. As a result, the energy dissipation per uncoded bit at Eb/No of 5 dB becomes 54 pJ/bit with an uncoded throughput of 45.5 Gbps under a postlayout simulation. This represents a 92% decrease in energy per bit and a 1143% in throughput increase with respect to our previous clockless LDPC decoder.
KW - Asynchronous circuits
KW - forward error control (FEC)
KW - iterative decoding
KW - low-density parity-check (LDPC) codes
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U2 - 10.1109/TCSI.2011.2107271
DO - 10.1109/TCSI.2011.2107271
M3 - Article
AN - SCOPUS:79960979682
VL - 58
SP - 1933
EP - 1943
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 8
M1 - 5712175
ER -
