Key technologies for 500-MHz VLSI system ultimate

Teruo Tamama, Naoaki Narumi, Tai ichi Otsuji, Masao Suzuki, Tsuneta Sudo

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Technologies needed for constructing ULTIMATE, including an 8-ps-resolution timing generator, a formatter with a real-time waveform control function, a 2.5-ps-resolution standard comparator, and a miniaturized 3-GHz 59-pole channel selector are described. Almost all the pin-electronics hardware has been integrated on twelve kinds of LSIs, eight of which are 2.5K-gate and 400-gate ultrahigh- speed bipolar gate arrays. ULTIMATE realizes ±55-ps overall timing accuracy by the timing calibration method which combines a standard comparator-based method and a TDR (time-domain reflectometry)-based method.

本文言語English
ホスト出版物のタイトルDigest of Papers - International Test Conference
出版社Publ by IEEE
ページ108-113
ページ数6
ISBN(印刷版)0818608706
出版ステータスPublished - 1988 12 1
外部発表はい

出版物シリーズ

名前Digest of Papers - International Test Conference
ISSN(印刷版)0743-1686

ASJC Scopus subject areas

  • 工学(全般)

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