The low-energy tilted ion implantation (I/I) for fin-type double-gate metal-oxide-semiconductor field-effect transistor (FinFET) source-drain (SD) extension doping is systematically investigated experimentally by fabricating a series of n+-polycrystalline silicon (poly-Si) gate n-channel FinFETs under different I/I conditions. The on-state current (ION) versus off-state current (IOFF) and the SD parasitic resistance (R p) are used for benchmarking the performance of the fabricated devices to investigate the optimal extension I/I conditions, including dose (D) and tilted angle (θ), at a fixed low energy of 5 keV. It is experimentally found that the best extension I/I conditions are D = 4 × 1014 cm-2 and θ = 60°. With further increasing D, the device performance deteriorates owing to the incomplete recrystallization of amorphous regions in the thin extension regions. In the case of θ = 0°, marked increment and fluctuations in Rp are observed because the implant atoms scatter out randomly from each extension region. The Rp value of the FinFETs fabricated under the above best I/I conditions is comparable to that of devices fabricated by the solid-phase diffusion of phosphors from phosphosilicate glass (PSG). This indicates that the extension I/I conditions of D = 4 × 1014 cm-2 and θ = 60° are almost optimal and is very effective for high-performance FinFET fabrication.
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