We propose an integrated neuron circuit for an asynchronous pulse neural network model. The circuit is suitable for an implementation of a wide range of spatio-temporal coding networks since the circuit can function as both a coincidence detector and an integrator of the input pulses by properly setting bias voltages. We fabricate a prototype chip for the proposed circuit using MOSIS HP/Agilent 0.5 μm CMOS semiconductor process. The experimental measurements from the chip confirm that the integrated neuron circuit qualitatively replicates the behavior of the model. Especially, coincidence detection of input pulses in a short-time window, and further, complex behavior including chaos in the internal state value and in the interspike intervals of the output pulses are illustrated.
|出版ステータス||Published - 2003 9 24|
|イベント||International Joint Conference on Neural Networks 2003 - Portland, OR, United States|
継続期間: 2003 7 20 → 2003 7 24
|Other||International Joint Conference on Neural Networks 2003|
|Period||03/7/20 → 03/7/24|
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