TY - GEN
T1 - Influence of fin height on poly-Si/PVD-TiN stacked gate FinFET performance
AU - Hayashida, T.
AU - Endo, Kazuhiko
AU - Liu, Y. X.
AU - O'uchi, S.
AU - Matsukawa, T.
AU - Mizubayashi, W.
AU - Migita, S.
AU - Morita, Y.
AU - Ota, H.
AU - Hashiguchi, H.
AU - Kosemura, D.
AU - Kamei, T.
AU - Tsukada, J.
AU - Ishikawa, Y.
AU - Yamauchi, H.
AU - Ogura, A.
AU - Masahara, M.
PY - 2011/12/20
Y1 - 2011/12/20
N2 - We experimentally investigated the device performance of n +- poly-Si/PVD-TiN stacked gate FinFETs with different H fin's. It was found that mobility enhances in the tall H fin devices due to the increased tensile stress. However, as L g decreases, I on for tall H fin case becomes worse probably due to high R sp. It was also confirmed that V th variation increases with increasing H fin due to the rough etcing of fin sidewall.
AB - We experimentally investigated the device performance of n +- poly-Si/PVD-TiN stacked gate FinFETs with different H fin's. It was found that mobility enhances in the tall H fin devices due to the increased tensile stress. However, as L g decreases, I on for tall H fin case becomes worse probably due to high R sp. It was also confirmed that V th variation increases with increasing H fin due to the rough etcing of fin sidewall.
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U2 - 10.1109/SOI.2011.6081800
DO - 10.1109/SOI.2011.6081800
M3 - Conference contribution
AN - SCOPUS:83455213488
SN - 9781612847597
T3 - Proceedings - IEEE International SOI Conference
BT - IEEE International SOI Conference, SOI 2011
T2 - 2011 IEEE International SOI Conference, SOI 2011
Y2 - 3 October 2011 through 6 October 2011
ER -