Independent-double-gate FINFET SRAM cell for drastic leakage current reduction

Kazuhiko Endo, Shin Ichi O'uchi, Yuki Ishikawa, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Meishoku Masahara, Junichi Tsukada, Kenichi Ishii, Eiichi Suzuki

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

The decreased feature size of metal-oxide-semiconductor (MOS) devices in ultra-large-scale-integrated circuits (ULSIs) requires the nano-scale complementary MOS (CMOS) fabrication technology. As silicon devices are scaled down to the nanometer regime, the device technology is facing to several difficulties. Standby power consumption in CMOS devices is now one of the most serious problem and becoming a limiting factor in MOSFET scaling [1]. Short channel effects (SCEs) such as threshold voltage (Vth ) roll off and sub-threshold slope (S-factor) degradation causes significant increased in power consumption. Catastrophic increase in static power consumption due to shot channel effects (SCEs) becomes the serious problem in future VLSI circuits. Especially, the leakage current in the SRAM array is the most critical issue for a low-power SoC because it occupies the considerable part of LSIs.

本文言語English
ホスト出版物のタイトルEmerging Technologies and Circuits
ページ67-79
ページ数13
DOI
出版ステータスPublished - 2010
外部発表はい
イベントInternational Conference on Integrated Circuit Design and Technology, ICICDT 2008 - Grenoble, France
継続期間: 2008 6 22008 6 4

出版物シリーズ

名前Lecture Notes in Electrical Engineering
2021 LNEE
ISSN(印刷版)1876-1100
ISSN(電子版)1876-1119

Other

OtherInternational Conference on Integrated Circuit Design and Technology, ICICDT 2008
国/地域France
CityGrenoble
Period08/6/208/6/4

ASJC Scopus subject areas

  • 産業および生産工学

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