The impacts of Cu contamination from a backside surface of a thinned wafer and Cu TSV in 3-D IC integration on device reliabilities are electrically evaluated by a transient capacitance measurement, which is called a capacitance-time (C-t) analysis. Intrinsic gettering (IG) layer, which was formed by high density oxygen precipitate shows excellent Cu retardation characteristics from the backside surface of the thinned wafer. Extrinsic gettering (EG) layer, which was formed by post-grinded dry polish (DP) treatment shows good Cu retardation characteristics compared to another post-grinded treatments. The minimal 30-nm thick Ta barrier layer in Cu via shows good barrier property to Cu diffusion from Cu via after annealing up to 60min at 300°C. However, it is not enough at 400°C annealing, because the generation lifetime shows significant degradation after the initial annealing for 5min. The DRAM cell characteristics show severe shortening retention time after an intentional Cu diffusion from the backside of the thinned DRAM chip at relatively low temperature of 300°C. The thermo-mechanical stress was produced during the bonding using high-density metal bumps because of the mismatch of coefficient of thermal expansion (CTE) among Si, Cu/Sn bump and organic under-fill. CuSn bump of 20-μm size has induced compressive stress of 140MPa beneath Si wafer surface, and it penetrates deeper area with large stress value after the bonding. The drain current and electron mobility of n-MOSFET which was located 15μm distance from metal bump are changed by ∼10 % due to the local tensile stress of 500MPa induced by micro bump. Electron mobility changed varying with the distance from metal bump. Influences of mechanical stress induced by Cu TSVs and metal bump-underill joining on device characteristics were also evaluated.
ASJC Scopus subject areas