TY - JOUR

T1 - Implementation and evaluation of a fine-grain Multiple-Valued Field Programmable VLSI based on Source-Coupled Logic

AU - Munirul, Haque Mohammad

AU - Hasegawa, Tomoaki

AU - Kameyama, Michitaka

PY - 2005/9/20

Y1 - 2005/9/20

N2 - This paper describes a design of a fine-grain Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) based on Multiple-Valued Source-Coupled Logic (MVSCL). An MV-FPVLSI consists of identical cells, each of which is connected to 8-neighborhood ones through 1-bit switch block for each direction. An arbitrary 2-variable binary logic operation is realized using threshold logic gates. Using 0.35μm standard CMOS design rule, a bit-serial adder is designed using the MV-FPVLSI. Using HSPICE simulation tools, a cell is evaluated and compared with corresponding binary implementation. Comparison results show that, under normalized power consumption better performance can be achieved if the linear summation with weight 1 of the input currents is possible. Moreover, the area of a cell can be reduced to 24% without any degradation in performance. That is, highly-parallel operations can be done using the MV-FPVLSI under total chip area constraint.

AB - This paper describes a design of a fine-grain Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) based on Multiple-Valued Source-Coupled Logic (MVSCL). An MV-FPVLSI consists of identical cells, each of which is connected to 8-neighborhood ones through 1-bit switch block for each direction. An arbitrary 2-variable binary logic operation is realized using threshold logic gates. Using 0.35μm standard CMOS design rule, a bit-serial adder is designed using the MV-FPVLSI. Using HSPICE simulation tools, a cell is evaluated and compared with corresponding binary implementation. Comparison results show that, under normalized power consumption better performance can be achieved if the linear summation with weight 1 of the input currents is possible. Moreover, the area of a cell can be reduced to 24% without any degradation in performance. That is, highly-parallel operations can be done using the MV-FPVLSI under total chip area constraint.

UR - http://www.scopus.com/inward/record.url?scp=24644485907&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=24644485907&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:24644485907

SP - 120

EP - 125

JO - Proceedings of The International Symposium on Multiple-Valued Logic

JF - Proceedings of The International Symposium on Multiple-Valued Logic

SN - 0195-623X

T2 - 35th International Symposium on Multiple-Valued Logic, ISMVL 2005

Y2 - 19 May 2005 through 21 May 2005

ER -