Impacts of Cu contamination on device reliabilities in 3-D IC integration

Kang Wook Lee, Ji Chel Bea, Yuki Ohara, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

研究成果: Article査読

13 被引用数 (Scopus)

抄録

The impacts of Cu contamination from a backside surface of a thinned wafer and Cu via on device reliabilities in 3-D IC integration are electrically evaluated. Intrinsic gettering (IG) layer, which was formed by high density oxygen precipitate, shows excellent Cu retardation characteristics from the backside surface of the thinned wafer. Extrinsic gettering (EG) layer, which was formed by postgrinded dry polish (DP) treatment shows good Cu retardation characteristics compared with other postgrinded treatments. The minimal 30-nm-thick Ta barrier layer in Cu via shows good barrier property to Cu diffusion from Cu via after annealing up to 60 min at 300 °C. However, it is not enough at 400 °C annealing, because the generation lifetime shows significant degradation after the initial annealing for 5 min. The DRAM cell characteristics show severe shortening retention time after an intentional Cu diffusion from the backside of the thinned DRAM chip at relatively low temperature of 300 °C.

本文言語English
論文番号6497564
ページ(範囲)451-462
ページ数12
ジャーナルIEEE Transactions on Device and Materials Reliability
14
1
DOI
出版ステータスPublished - 2014 3

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

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