Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

Kangwook Lee, Seiya Tanikawa, Hideki Naganuma, Jichoru Be, Mariappine Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ∼ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.

本文言語English
ホスト出版物のタイトル2014 IEEE International Reliability Physics Symposium, IRPS 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(印刷版)9781479933167
DOI
出版ステータスPublished - 2014 1 1
イベント52nd IEEE International Reliability Physics Symposium, IRPS 2014 - Waikoloa, HI, United States
継続期間: 2014 6 12014 6 5

Other

Other52nd IEEE International Reliability Physics Symposium, IRPS 2014
CountryUnited States
CityWaikoloa, HI
Period14/6/114/6/5

ASJC Scopus subject areas

  • Engineering(all)

フィンガープリント 「Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル