Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs

Tomohiro Yoshida, Kengo Kobayashi, Taiichi Otsuji, Tetsuya Suemitsu

研究成果: Conference contribution

抄録

We report an impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs). Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different height in the stems of T-gates reveals that the parasitic gate delay decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more freedom to use the T-gate electrode with a large head in the devices for high-voltage applications.

本文言語English
ホスト出版物のタイトルESSDERC 2013 - Proceedings of the 43rd European Solid-State Device Research Conference
出版社IEEE Computer Society
ページ115-118
ページ数4
ISBN(印刷版)9781479906499
DOI
出版ステータスPublished - 2013 1 1
イベント43rd European Solid-State Device Research Conference, ESSDERC 2013 - Bucharest, Romania
継続期間: 2013 9 162013 9 20

出版物シリーズ

名前European Solid-State Device Research Conference
ISSN(印刷版)1930-8876

Conference

Conference43rd European Solid-State Device Research Conference, ESSDERC 2013
CountryRomania
CityBucharest
Period13/9/1613/9/20

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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