Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs

Tomohiro Yoshida, Kengo Kobayashi, Taiichi Otsuji, Tetsuya Suemitsu

研究成果: Article査読

7 被引用数 (Scopus)


The impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs) is studied. Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different stem height of T-gates reveals that the parasitic gate delay time decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more flexibility to use the T-gate electrode with a large head in the devices for high-voltage applications.

ジャーナルSolid-State Electronics
出版ステータスPublished - 2014 12

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 凝縮系物理学
  • 電子工学および電気工学
  • 材料化学


「Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。