Impact of mechanical stress control on VLSI fabrication process

Shuji Ikeda, Yasuhide Hagiwara, Hideo Miura, Hiroyuki Ohta

研究成果: Conference article査読

26 被引用数 (Scopus)

抄録

Fabrication process is designed to minimize mechanical stress in semiconductor devices and to improve device reliability. Mechanical stress levels were predicted by simulation then TEM analysis was performed to evaluate critical stress that generates dislocations. This gives us design guidelines for small geometry LOCOS process. Polysilicon thickness in the W polycide gate electrode is designed to minimize mechanical stress in the gate oxide and to suppress gate oxide failure in probe and class tests. Moreover, critical stress to generate dislocations during post source / drain ion implantation anneal is obtained by a ball indentation method. This indicated that lower temperature anneal is effective to suppress dislocations. Two-step anneal is introduced to suppress dislocations to enable higher ion activation.

本文言語English
ページ(範囲)77-80
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 1996 12 1
外部発表はい
イベントProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
継続期間: 1996 12 81996 12 11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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