IC implementation of a current-mode chaotic neuron

Ruben Herrera, Ken Suyama, Yoshihiko Horio

研究成果: Article査読

5 被引用数 (Scopus)

抄録

An IC implementation of a new current-mode chaotic neuron is presented. The circuit mainly consists of CMOS inverters, which are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using 1.2 μm HP CMOS process. One neuron occupies only 0.0076 mm2, which is smaller than a standard bonding pad. The circuit was tested at a clock frequency of 2 MHz.

本文言語English
ページ(範囲)546-549
ページ数4
ジャーナルUnknown Journal
3
出版ステータスPublished - 1998
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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