Hot-carrier reliability in submicron pMOSFETs

M. Koyanagi, T. Huang, A. Lewis, J. Y. Chen

研究成果: Paper査読

抄録

Degradation of device characteristics due to hot-carrier injection in submicron pMOSFETs (p-metal-oxide-semiconductor field-effect transistors) is discussed. pMOSFETs suffer significantly from enhanced device degradation in the submicron range due to the hot-electron-induced-punchthrough (HEIP) effect, the swapped pulse stress, and the gate-induced drain leakage current. As a result, the hot-carrier lifetime of pMOSFETs becomes shorter than that of LDD (lightly doped drain) nMOSFETs. Therefore, use of the LDD structure is essential in submicron pMOSFETs at 5-V supply voltage. The use of surface-channel pMOSFETs with p+ poly gate would mitigate the hot-carrier-induced device degradation if problems inherent to p+ poly gate were solved. The use of a gate-drain-overlapped LDD structure might become necessary in sub-half-micron pMOSFETs to improve the hot-carrier reliability without sacrificing the device performance.

本文言語English
ページ312-316
ページ数5
出版ステータスPublished - 1989 12 1
イベントInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan
継続期間: 1989 5 171989 5 19

Other

OtherInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers
CityTaipei, Taiwan
Period89/5/1789/5/19

ASJC Scopus subject areas

  • Engineering(all)

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