Highly scalable 3-D vertical FG NAND cell arrays using the Sidewall Control Pillar (SCP)

Moon Sik Seo, Jong Moo Choi, Sung Kye Park, Tetsuo Endoh

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

In this paper, we propose a novel 3-dimensional (3-D) vertical floating gate (FG) type NAND flash memory cell arrays using the sidewall control pillar (SCP). This novel cell consists of cylindrical FG and SCP with a line type control gate (CG) structure. For simplifying the process flow, we propose to fabricate the cylindrical SCP structure by using the self-aligned process with the deposition of the poly silicon pillar. In order to compensate the increase of the channel capacitance, we decrease the floating gate width by about 15nm, which is comparable thickness to recent charge trap layer, and adopt the high-k material for inter poly dielectric (IPD). As a result, we successfully demonstrate the program with 18V at Vth=4V and erase with 17V at Vth=-3V, that are comparable performances in comparison with the conventional FG NAND cells by using the device simulator. Moreover, using the proposed SCP NAND cell, the interference margin with cell space length has been successfully extended and the same vertical scaling as the charge trap (CT) type 3D NAND cell also can be realized for 2Xnm technology. Above all, the proposed cell has good potential for Terabit 3-D vertical NAND cell with high manufacturability.

本文言語English
ホスト出版物のタイトル2012 4th IEEE International Memory Workshop, IMW 2012
DOI
出版ステータスPublished - 2012
イベント2012 4th IEEE International Memory Workshop, IMW 2012 - Milano, Italy
継続期間: 2012 5月 202012 5月 23

出版物シリーズ

名前2012 4th IEEE International Memory Workshop, IMW 2012

Other

Other2012 4th IEEE International Memory Workshop, IMW 2012
国/地域Italy
CityMilano
Period12/5/2012/5/23

ASJC Scopus subject areas

  • 電子工学および電気工学

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