Highly parallel collision detection VLSI processor for intelligent robots

Michitaka Kameyama, Tadao Amada, Tatsuo Higuchi

研究成果: Paper査読

1 被引用数 (Scopus)

抄録

A collision detection VLSI processor is proposed for achieving ultrahigh performance processing with an ideal parallel processing scheme. Coordinate transformation and inference check in 3-dimensional task space are fully utilized in the processing algorithm, so that direct collision detection can be executed with VLSI-oriented regular data flow. The structure of the processing element (PE) is very simple because a coordinate rotation digital computer (CORDIC) arithmetic unit for coordinate transformation and a few memories are included as the main components. Evaluation shows that the chip can be developed with a reasonable size of 5.1 × 12.7 mm2 and the typical collision detection time is about 384 μsec using 100 PEs. The performance is about ten thousand times faster than that of the conventional approach using general-purpose processors.

本文言語English
ページ29-30
ページ数2
出版ステータスPublished - 1991 12 1
イベント1991 Symposium on VLSI Circuits - Oiso, Jpn
継続期間: 1991 5 301991 6 1

Other

Other1991 Symposium on VLSI Circuits
CityOiso, Jpn
Period91/5/3091/6/1

ASJC Scopus subject areas

  • 工学(全般)

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