A collision detection VLSI processor is proposed for achieving ultrahigh performance processing with an ideal parallel processing scheme. Coordinate transformation and inference check in 3-dimensional task space are fully utilized in the processing algorithm, so that direct collision detection can be executed with VLSI-oriented regular data flow. The structure of the processing element (PE) is very simple because a coordinate rotation digital computer (CORDIC) arithmetic unit for coordinate transformation and a few memories are included as the main components. Evaluation shows that the chip can be developed with a reasonable size of 5.1 × 12.7 mm2 and the typical collision detection time is about 384 μsec using 100 PEs. The performance is about ten thousand times faster than that of the conventional approach using general-purpose processors.
|出版ステータス||Published - 1991 12 1|
|イベント||1991 Symposium on VLSI Circuits - Oiso, Jpn|
継続期間: 1991 5 30 → 1991 6 1
|Other||1991 Symposium on VLSI Circuits|
|Period||91/5/30 → 91/6/1|
ASJC Scopus subject areas