Highly manufacturable 0.18 um generation LOGIC technology

Shuji Ikeda, Y. Yoshida, K. Shoji, K. Kuroda, K. Komori, N. Suzuki, K. Okuyama, S. Kamohara, N. Ishitsuka, H. Miura, E. Murakami, T. Yamanaka

研究成果: Conference article査読

5 被引用数 (Scopus)


A 0.18 um generation logic technology has been developed with 0.14 um gate length transistors. Guidelines to suppress mechanical stress in Shallow Trench Isolation are clearly described. Stable Co salicide process has been integrated with the combination of NO treated gate oxide and BF2 source drain ion implantation. Amorphous Si with RTA is key to control grain size and suppress large variation of drain current in small size transistors. Two kinds of metallization systems, aluminum with SiOF dielectrics and dual damascene Cu are developed in same layout rule.

ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 1999 12月 1
イベント1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA
継続期間: 1999 12月 51999 12月 8

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 凝縮系物理学
  • 電子工学および電気工学
  • 材料化学


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