Highly dependable 3-D stacked multicore processor system module fabricated using reconfigured multichip-on-wafer 3-D integration technology

K. W. Lee, H. Hashimoto, M. Onishi, S. Konno, Y. Sato, C. Nagai, J. C. Bea, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi

研究成果: Conference contribution

抄録

A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.

本文言語English
ホスト出版物のタイトル2014 IEEE International Electron Devices Meeting, IEDM 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ページ28.6.1-28.6.4
February
ISBN(電子版)9781479980017
DOI
出版ステータスPublished - 2015 2月 20
イベント2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States
継続期間: 2014 12月 152014 12月 17

出版物シリーズ

名前Technical Digest - International Electron Devices Meeting, IEDM
番号February
2015-February
ISSN(印刷版)0163-1918

Other

Other2014 60th IEEE International Electron Devices Meeting, IEDM 2014
国/地域United States
CitySan Francisco
Period14/12/1514/12/17

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 凝縮系物理学
  • 電子工学および電気工学
  • 材料化学

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