High throughput/gate FN-based hardware architectures for AES-OTR

Rei Ueno, Naofumi Homma, Tomonori Iida, Kazuhiko Minematsu

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

This paper presents high throughput/gates Feistel network (FN)-based AES-OTR hardware architectures. AES-OTR is an authenticated encryption (AE) scheme as a block cipher mode of operation using AES. While AES-OTR is one of the most theoretically efficient AEs using AES and has superior features, its practical efficiency in hardware is unclear due to no known reports of its hardware implementation. In this paper, we present efficient AES-OTR hardware architectures. In contrast to conventional AE architectures, our architecture forms the 2-round FN of OTR, which makes it easy to integrate the peripheral into hardware for OTR operations. The proposed architectures had 2.4 and 13.5 times higher throughput/gates than the de facto standard AE (i.e., AES-GCM) core on FPGA and ASIC, respectively, through logic syntheses.

本文言語English
ホスト出版物のタイトル2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781728103976
DOI
出版ステータスPublished - 2019
イベント2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
継続期間: 2019 5 262019 5 29

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
2019-May
ISSN(印刷版)0271-4310

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
国/地域Japan
CitySapporo
Period19/5/2619/5/29

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「High throughput/gate FN-based hardware architectures for AES-OTR」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル