High throughput parallel arithmetic circuits for fast fourier transform

Ryosuke Nakamoto, Sakae Sakurabaf, Alexandra Martins, Takeshi Onomi, Shigeo Satof, Koji Nakajima

研究成果: Article査読

抄録

We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.

本文言語English
ページ(範囲)280-287
ページ数8
ジャーナルIEICE Transactions on Electronics
E94-C
3
DOI
出版ステータスPublished - 2011 3

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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