High-throughput bit-serial LDPC decoder LSI based on multiple-valued asynchronous interleaving

Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet

研究成果: Article査読

11 被引用数 (Scopus)

抄録

This paper presents a high-throughput bit-serial lowdensity parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90 nm CMOS technology, at a comparable BER.

本文言語English
ページ(範囲)867-874
ページ数8
ジャーナルIEICE Transactions on Electronics
E92-C
6
DOI
出版ステータスPublished - 2009 1 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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