High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit

研究成果: Conference contribution

抄録

A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current-mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.

本文言語English
ホスト出版物のタイトルProceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
ページ70-75
ページ数6
DOI
出版ステータスPublished - 2008 9 3
イベント38th International Symposium on Multiple-Valued Logic, ISMVL 2008 - Dallas, TX, United States
継続期間: 2008 5 222008 5 24

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other38th International Symposium on Multiple-Valued Logic, ISMVL 2008
国/地域United States
CityDallas, TX
Period08/5/2208/5/24

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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