抄録
A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS masterslice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good P//e performance (4. 2 db net coding gain at P//e equals 1 multiplied by 10** minus **6), reduction of power consumption and number of gates with low development costs.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 491-493 |
| ページ数 | 3 |
| ジャーナル | Electronics Letters |
| 巻 | 22 |
| 号 | 9 |
| 出版ステータス | Published - 1986 1月 1 |
ASJC Scopus subject areas
- 電子工学および電気工学