In this paper a pass-transistor logic (PTL) using Surrounding Gate Transistor (SGT) is reported for the first time. This SGT-based PTL brings out the latent abilities of the PTL, especially improvement of the area occupation by 74% and the power-delay product by 70% at the supply voltage of IV compared to bulk MOSFET-based PTL.
|出版ステータス||Published - 2000 1 1|
|イベント||International Conference on Simulation of Semiconductor Processes and Devices - Seattle, WA, USA|
継続期間: 2000 9 6 → 2000 9 8
|Other||International Conference on Simulation of Semiconductor Processes and Devices|
|City||Seattle, WA, USA|
|Period||00/9/6 → 00/9/8|
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