High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs

K. W. Lee, J. C. Bea, T. Fukushima, Y. Ohara, T. Tanaka, M. Koyanagi

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even after the initial annealing for 5 min at 300°C. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. However, the C-t curves of the trench capacitors with 100-nm thick Ta layer exhibit no change after annealing up to 60min. Based on the C-t evaluation results, we developed high reliable and fine-size of 5-μm diameter backside Cu TSV to achieve high reliability and high-end 3-D LSIs.

本文言語English
ホスト出版物のタイトル2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOI
出版ステータスPublished - 2011 12月 1
イベント2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan
継続期間: 2012 1月 312012 2月 2

出版物シリーズ

名前2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Other

Other2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
国/地域Japan
CityOsaka
Period12/1/3112/2/2

ASJC Scopus subject areas

  • 制御およびシステム工学

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