This paper presents a unified approach for designing high-radix dividers for on-line signal and data processing applications. It has long been recognized that the use of higher radices makes possible the reduction of computational steps in division process. However, most of the conventional high-radix algorithms are not suited for designing high-speed parallel dividers since they require look-up tables for selecting quotient digits. In this paper, we present a high-radix divider design that does not assume the use of look-up tables and is applicable to arbitrary radices. By prescaling the operands and converting the representation of each partial remainder into partially non-redundant representation, the quotient digit can be obtained directly from the integer part of the partial remainder. This paper also discusses the design of a radix-8 fully parallel divider as an example.
|出版ステータス||Published - 1996 1月 1|
|イベント||Proceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing - San Francisco, CA, USA|
継続期間: 1996 10月 30 → 1996 11月 1
|Other||Proceedings of the 1996 9th IEEE Workshop on VLSI Signal Processing|
|City||San Francisco, CA, USA|
|Period||96/10/30 → 96/11/1|
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