High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph

N. Ohsawa, M. Hariyama, M. Kameyama

研究成果: Conference contribution

13 被引用数 (Scopus)

抄録

This paper proposes a high-performance field programmable VLSI processor (FPVLSI), in which a bit-serial processing element (PE) array is introduced to reduce the complexity of programmable interconnection networks. Therefore, the area and delay of a switch block in the interconnection network can be greatly reduced. Moreover, direct allocation of a control/data flow graph is employed where only a single node is mapped into a PE so that the wiring complexity is greatly reduced. The FPVLSI with 4400 PEs is designed in a 0.35 μm CMOS process. The performance of the FPVLSI is evaluated to be 28 times higher than that of the typical FPGA when executing the 16-point FFT.

本文言語English
ホスト出版物のタイトルProceedings - IEEE Computer Society Annual Symposium on VLSI
ホスト出版物のサブタイトルNew Paradigms for VLSI Systems Design, ISVLSI 2002
編集者Asim Smailagic, Robert Brodersen
出版社IEEE Computer Society
ページ95-100
ページ数6
ISBN(電子版)0769514863
DOI
出版ステータスPublished - 2002 1 1
イベントIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002 - Pittsburgh, United States
継続期間: 2002 4 252002 4 26

出版物シリーズ

名前Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
2002-January
ISSN(印刷版)2159-3469
ISSN(電子版)2159-3477

Other

OtherIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002
国/地域United States
CityPittsburgh
Period02/4/2502/4/26

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 制御およびシステム工学
  • 電子工学および電気工学

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